VLSI 2010 Annual Symposium

<p>1. Intelligent NOC Hotspot Prediction.- 2. Accurate Asynchronous Network-on-Chip Simulation Based on a Delay-Aware Model.- 3. Trust Management Through Hardware Means: Design Concerns and Optimizations.- 4. MULTICUBE: Multi-Objective Design Space Exploration of Multi-Core Architectures.- 5. 2PARMA: Parallel Paradigms and Run-time Management Techniques for Many-Core Architectures.- 6. Adaptive Task Migration Policies for Thermal Control in MPSoCs.- 7. A High Level Synthesis Exploration Framework with Iterative Design Space Partitioning.- 8. A Scalable Bandwidth Aware Architecture for Connected Component Labelling.- 9. The SATURN Approach to SysML-based HW/SW Codesign.- 10. Mapping Embedded Applications on MPSoC - The MNEMEE approach.- 11. The MOSART Mapping Optimisation for Scalable Multi-core ARchiTecture.- 12. XMSIM: EXtensible Memory SIMulator for Early Memory Hierarchy Evaluation.- 13. Self-Freeze Linear Decompressors: Test Pattern Generators for Low Power Scan Testing.- 14. SUT-RNS Forward and Reverse Converters.- 15. Off-Chip SDRAM Access Through Spidergon STNoC.- 16. Digital Microfluidic Biochips: A Vision for Functional Diversity and More than Moore.- 17. FPGA Startup through Sequential Partial and Dynamic Reconfiguration.- 18. Two Dimensional Dynamic Multigrained Reconfigurable Hardware.- 19. System Level Design for Embedded Reconfigurable Systems using MORPHEUS Platform.- 20. New Dimensions in Design Space and Runtime Adaptivity for Multiprocessor Systems through Dynamic and Partial Reconfiguration: The RAMPSoC Approach. </p>