ASIC Design and Synthesis

RTL Design Using Verilog

Gebonden Engels 2021 9789813346413
Verwachte levertijd ongeveer 9 werkdagen

Samenvatting

This book describes simple to complex ASIC design practical scenarios using Verilog. It builds a story from the basic fundamentals of ASIC designs to advanced RTL design concepts using Verilog. Looking at current trends of miniaturization, the contents provide practical information on the issues in ASIC design and synthesis using Synopsys DC and their solution. The book explains how to write efficient RTL using Verilog and how to improve design performance. It also covers architecture design strategies, multiple clock domain designs, low-power design techniques, DFT, pre-layout STA and the overall ASIC design flow with case studies. The contents of this book will be useful to practicing hardware engineers, students, and hobbyists looking to learn about ASIC design and synthesis.

Specificaties

ISBN13:9789813346413
Taal:Engels
Bindwijze:gebonden
Uitgever:Springer Nature Singapore

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Inhoudsopgave

<p>Chapter 1. Introduction.- Chapter&nbsp;2. Design using CMOS.- Chapter&nbsp;3. ASIC design synthesis for combinational design (RTL using VHDL).- Chapter&nbsp;4. ASIC Design and synthesis of complex combinational logic (RTL using VHDL).- Chapter&nbsp;5. ASIC Design and synthesis of sequential logic (RTL using VHDL).- Chapter&nbsp;6. ASIC design guidelines.- Chapter&nbsp;7. ASIC RTL Verification.- Chapter&nbsp;8. FSM using VHDL and synthesis.- Chapter&nbsp;9. ASIC design improvement techniques.- Chapter&nbsp;10. ASIC Synthesis using Synopsys DC.- Chapter&nbsp;11. Design for Testability.- Chapter&nbsp;12. Static timing analysis.- Chapter&nbsp;13. Multiple Clock domain designs.- Chapter&nbsp;14. Low power ASIC design.- Chapter&nbsp;15. ASIC Physical design.</p><p></p>

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